1. Field of the invention
The invention relates to manufacturing methods of semiconductor devices and, more particularly, to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and a method for manufacturing the same.
2. Description of Related Art
As shown in FIG. 1, the superjunction MOSFET (metal oxide semiconductor field effect transistor) adopts a new voltage-withstanding structure consisting of a series of alternately arranged P-type and N-type semiconductor thin layers. At off state, both P-type and N-type charges can be fully depleted at relative low voltage by charge compensation. Thereby high breakdown voltage can be realized even the impurity concentration in P-type and N-type doping region is high. And low on-resistance of the device can be realized because the impurity concentration of doping region is several times as that in conventional MOSFET. Therefore the device performance of the superjunction MOSFET can break the silicon limit of the conventional MOSFET (cf, Hu. C., Rec. Power Electronics Specialists Conf., San Diego, (1979), P 385).
Currently, there are two ways to manufacture the new voltage-withstanding structure consisting of a series of alternately arranged P-type and N-type semiconductor thin layers. One way is multiple epitaxial process: it uses multiple epitaxial film deposition, lithography and implantation to get alternately arranged P-type and N-type doping region. The other way is trench process: it etches a trench first, and then either fills the trench with conducting silicon or does tilted implanting to the trench sidewall. The multiple epitaxial process is a complicated process with high cost, and it is difficult to control. For the trench process, the tilted implanting process has poor stability and repeatability for mass production. Therefore, the silicon filling option is attracting more and more attention. For the silicon filling option, the key process is doing silicon film deposition to fill the trench and then get the silicon outside of the trench removed by CMP (chemical physical polishing). It was reported that epitaxial single crystal silicon can be used as the filling material. However, for a trench with the depth of 40-50 μm or deeper, this epitaxial filling process has many drawbacks, such as high time cost, technical difficulties, because the void free epitaxial film is hard to realize for high aspect ratio trench (aspect ratio is higher than 5). Moreover, during production, the inline process control on both impurity concentration and the defects is hard, because when the epitaxial film fills the trench, the monitor method for blank epitaxial defects and impurity concentration will not apply. It is reported that doped polysilicon can be used to fill the trench, but normally only high concentration impurity at the range of E18-E20 atoms/cm3 can be realized by current tool such as a furnace. This concentration level is too high for high voltage devices whose doping concentration of voltage withstand layer is about E15-E17 atoms/cm3. If the current furnace is used to get polysilicon at relatively low concentration impurity at the range of E15-E17 atoms/cm3, only a portion of the furnace can be effectively used because of the non-uniformity within the furnace. Therefore the productivity of the furnace is low.